Abstract:
The microcomputer architecture named BZK.SAU.FPGA, which was developed in 2014, was used to increase efficiency in the teaching of the Computer Architecture and Organization course, which is one of the basic courses of the Department of Computer Engineering. In the last version released in 2018, the architecture has been started to be used in many engineering disciplines with its modular structure and a basic operating system. However, this architecture uses fixed-point numbers in arithmetic operations. Although this situation contributes to its use as an educational tool at the beginner level for new learners, the fact that it cannot operate with floating point numbers is one of the biggest shortcomings of the educational tool. Floating point numbers are used extensively in applications such as mathematical analysis, signal processing, image processing, and so on. Therefore, in this study, the FPA unit for the computation of addition, subtraction, multiplication, and division operations is integrated into this architecture. For FPA unit implementation, an assembly-level program has been embedded in the architecture using an IEEE-754 half-precision binary format (FP16) with the aim of presenting the fundamental of the floating-point computation. The FPA unit proposed to observe the behavior of floating point numbers in arithmetic operations and increase awareness of these issues was used as an auxiliary tool in the computer architecture course. A pre- and postsurvey study was conducted to see the learning outcomes of students using this tool on floating point numbers. We found a significant association between pre- and postsurvey, indicating that students' knowledge about the behavior of floating point numbers increased (p < .001).
